A vector processor is used for a vector process in which a certain computation is performed in a repetition to a large amount of data in arrays (for example, U.S. Pat. No. 5,809,552). By the vector processor, data elements in an array are consecutively processed under one instruction, and a high computation throughput is obtained. The vector processor has, for example, load/store and computation pipelines. The load/store pipeline reads data elements from a data memory, and stores the data elements in a register (referred to as a vector register, hereinafter) in a processing order of the computation pipeline. The computation pipeline, fetching and decoding a computation instruction for one time, reads data elements consecutively in a sequence from the vector register, and performs an arithmetic computation or the like. Then, the computation pipeline stores the data elements indicating the computation results into the vector register in the processing order. Then, the load/store pipeline reads the data elements indicating the computation results from the register, and stores the data elements in the data memory in the processing order.
There is a case that, for example, in a large-capacity data memory such as a DRAM (Dynamic Random Access Memory), data elements for input are stored at discontinuous addresses. Or, there is a case that the data elements indicating computation results will be stored at discontinuous addresses of the data memory. When the load/store pipeline reads the data elements from the data memory into the vector register, and/or writes the data elements from the vector register into the data memory, there occur accesses to a wide range of the memory area. This increases latency, which can be a factor to strangle the throughput. Also, for example, in pipelining with a high-speed cache memory such as SRAM (Static Random Access Memory) between the data memory and the vector register so as to decrease the latency, there is a concern for an increasing circuit scale and a high production cost.